As a technique of a semiconductor device has been rapidly developed for decades, the integration of a semiconductor memory element has been increased. In case of a DRAM (Dynamic Random Access Memory), the number of semiconductor memory elements integrated in one silicon substrate reached billions. The number of increased semiconductor memory elements requests the increase of a power consumption, and the reduction of an operation speed caused by a parasitic effect. However, due to characteristics of a semiconductor substrate material or a semiconductor package material, it is difficult to accept the increase of the power consumption. Thus, a circuit designer has lowered a power voltage supplied from an external device to an integrated circuit, or has made an internal power voltage lower than an external power voltage. A lower internal power voltage allows a low voltage swing of a circuit and reduces a dynamic current consumption. This is efficient in a circuit for driving a long data line. A dynamic current consumption of a distribution line (IL) is in proportion to the multiple of a capacitive load (CL) of the power distribution line and a variation ratio (dV/dt) of a voltage applied to the power distribution line as expressed in an equation 1.IL=CL(dV/dt),  Equation 1
Although the integration of a semiconductor memory device is increased, a parasitic element, e.g., a parasitic resistance or a parasitic capacitive load, which is caused by the increase of the distribution lines made of a metal or a poly-silicon, may be not reduced. Especially, this problem may be intensified as the integration of a semiconductor memory device increase. For example, if the integration of a semiconductor memory device increases from 1 Giga byte DRAM to 4 Giga byte DRAM, a parasitic element increases theoretically as four times since a length of a power distribution line increases as four times. In fact, due to the development of a minimization technique trend of a semiconductor manufacturing process, the parasitic element does not increase as many times as theoretically. If a linewidth is minimized, since a parasitic capacitance per a unit length is reduced but a parasitic resistance per a unit length increases, a total response time depending on a time constant as a multiple of a resistance R and a capacitance C increases according as the integration of a semiconductor memory device increases.
A reduction of an operation speed and an increase of a power consumption are intensified in a semiconductor memory device, and are exposed in a technique where a plurality of substrates are stacked in a three-dimensional. This problem will be described in details.
A semiconductor memory device includes memory cells for storing information, which are arrayed in a row line and a column line.
As the integration of a semiconductor memory device increases, a parasitic resistance and a parasitic capacitance on a path of binary information increases.
FIG. 1a illustrates a conventional packaged stack structure where a plurality of substrates are coupled to each other by a wire bonding. The problem will be described in this case. FIG. 1a shows a cross section view of a multiple package 100 having a plurality of semiconductor substrates, which are stacked, and each of the plurality of semiconductor substrates 101, 103 and 105 is coupled to each other by a wire bonding. If each of the plurality of semiconductor substrates is a semiconductor memory device, each of the plurality of semiconductor substrates may include a block as shown in FIG. 2.
FIG. 2 illustrates a block including four banks 111 to 114. Each of four banks 111 to 114 includes 32 matrixes MAT_0 to MAT_31. One of 32 matrixes MAT_0 to MAT_31 includes memory cells for storing binary information which are arrayed in a row direction and a column direction. FIG. 2 illustrates an example of a semiconductor memory device having arrayed matrixes. One of the plurality of matrixes will be shown in details in FIG. 3.
The matrix includes memory cells MC of which each is arrayed in a row direction and a column direction. A bit line is commonly coupled to a memory cell in a column direction, and binary information is read or written. The binary information written in a memory cell is transferred by a path of sequence of an input/output (I/O) circuit, a local data line, a bit line and a memory cell through a package or a pin coupled to an external device of a semiconductor substrate. A read path sequence is opposite to a write path sequence.
A parasitic element which exists in a read path or a write path is equivalently shown in FIG. 4.
If it is assumed that a length of a bit line is 400 μm (micro-meter) and FIG. 3 illustrates a semiconductor memory device 101 of a first substrate, and a capacitance per unit μm is 1 nF (nano-Farad), a total capacitance CBIT of a bit line is 0.4 pF (pico-Farad). In general, since a length of a local data line is long as a length of a bit line by ten times, the total capacitance CLOC of the local data line is 4 pF. If a length of a global data line is long as a length of a bit line by five times, the total capacitance CGLO of the global data line is 20 pF. If binary information is transferred sequentially via the bit line, the local data line and the global data line, 0.4 pF, 4 pF and 20 pF are sequentially charged or discharged, and this represents the increase of a propagation delay time of data. The propagation delay time is in proportion to a time constant of the path. For the convenience of calculation, if it is assumed that a total parasitic resistance element of the path is 10 ohm, the time constant of the path is 244 ps (pico-second)
Meanwhile, in view of a power consumption, when one cycle is 4 ns (nano-second), if a voltage variation of the data line is 1.2 V (voltage), a dynamic current consumption is 1.2 mA (mill-Ampere) by the equation 1. Herein, if the data has 32 bits, the total number of data lines having a pair is 64. In conclusion, during the one cycle, a total dynamic current which is consumed in a pair of data lines having 32 bits is 76.8 mA, which is greater than 1.2 mA by 64 times. Since a parasitic capacitance CPKG caused by a lead frame of a package or a wire bonding is several pico-Farads pF or dozen pico-Farads pF, the above-described problems will be deteriorated.
As shown in FIG. 1b, these problems do not disappear although a plurality of substrates of the semiconductor memory device are penetrated through a TSV (through silicon via). But, these problems may be reduced as much as the increased amount of the power consumption or the propagation delay time due to the parasitic element CPKG caused by a lead frame of a package or a wire bonding.
Thus, in a semiconductor memory device or a semiconductor device provided by stacking a plurality of substrates, the increase of an operation and the reduction of a power consumption are requested through the reduction of the propagation delay time.